How does weighted registor DAC work?

Following is the basic diagram for weighted registor DAC.

Here V1 is MSB (most significant bit) and V4 is LSB (least significant bit). For above circuit, minimum resistance is 1k Ohm. weights used are 1, 2, 4, 8 and so on (if more bits are present). Now we will apply superposition theorem.

Current output due to V1 is V1/1K

Similarly current outputs due to V2, V3, V4 are,

V2/2K,

V3/4K,

V4/8K respectively.

Since total output is addition of all independent outputs,

Iout = V1/1K + V2/2K + V3/4K + V4/8

Iout = (V1/1 + V2/2 + V3/4 + V4/8)/1K

i.e.

Iout = 8 * (V1*8 + V2*4 + V3*2 + V1*1)/1K

We represent digital signal in binary format and analog signal in decimal format. For converting binary number system into decimal number system we multiply each bit of binary system by increasing power of 2 from LSB to MSB. Which is obtained in above equation. Thus Iout represent the analog signal. Now suppose if load resistance is RL then Voltage output is calculated as,

Vout = RL * Iout

Vout = 8 * RL * (V1*8 + V2*4 + V3*2 + V4*1)/1K

Thus Vout represent the analog signal with multiplication factor 8*RL/1K.

In this way weighted registor Digital to analog converter works.

But there is a catch, when we connect RL as load registor, while calculating currents using superposition theorem, RL will come in series across R4, R3, R2, R1 for inputs V1, V2, V3, V4. This will change the output currents. And due to that we won't get multiplication factors as 1, 2, 4, 8, ... This will produce error for converting binary number system to digital number system i.e. digital signal to analog signal. For this drawback, we can have following 3 possible solutions,

1. Take RL so high that there will be negligible voltage drop and RL will act as open circuit. This will minimize the error.
2. For given RL, choose R1, R2, R3, R4 such that, R1+RL:R2+RL:R3+RL:R4+RL are in the ration 1:2:4:8
3. connect buffer between load and DAC so that RL will have zero effect upon input current.

Solution 1 and 2 has drawbacks that we cannot always have infinite load resistance and it is difficult to get odd valued registors respectively. Thus solution 3 is preferred in which OPAMP can be used as a buffer circuit.